1. Field of the Invention
The present invention relates to an electrostatic discharge protection circuit. More particularly, the present invention relates to an electrostatic discharge protection circuit with a bypass circuit having a plurality of bipolar transistors connected in stack.
2. Description of the Related Art
In recent years, the integration of semiconductor devices advances by reducing the line width and increasing the number of stacked film layers. For example, in the metal-oxide-semiconductor (MOS) devices, the thickness of the gate oxide layer is reduced and the length of the channel is shortened as the MOS device is miniaturized. Furthermore, thickness of the junction between source and drain is reduced and the source/drain region is fabricated using the lightly doped drain (LDD) method. However, as the dimensions of integrated circuits (IC) are gradually reduced, the tolerance of current diminishes correspondingly. Therefore, the smaller the size of integrated circuits, the larger the damages caused by electrostatic discharge (ESD).
In general, the waveform of electrostatic discharge has a profile of a relatively large voltage (around 2000V) or current (around 1.3 Amp) within a very short rise time (often between 1 ns to 15 ns). Hence, if the integrated circuit receives electrostatic discharge suddenly, the integrated circuit may be burnt, damaged or punched through.
To prevent the damage of ESD to the integrated circuit, an electrostatic discharge protection circuit is normally installed between the highest voltage input terminal (VDD) and the lowest voltage input terminal (VSS) of the integrated circuit for bypassing most of the ESD current. Therefore, the ESD current are avoided to pass through the integrated circuit.
FIG. 1 is a circuit diagram of a conventional ESD protection circuit. As shown in FIG. 1, the ESD protection circuit 100 including a gate-grounded N-type metal-oxide-semiconductor (GGNMOS) transistor 108 is connects with an integrated circuit 102 and two input pads 104 and 106 of the integrated circuit 102. The pad 104 is connected to an input voltage VDD and the drain of the NMOS transistor 108, and the other pad 106 is connected to input voltage VSS and the source, the gate and the substrate of the NMOS transistor 108. In general, the voltage VSS is a ground voltage. Therefore, when the ESD voltage received by the pad 104 is higher than that received by the pad 106, the parasitic bipolar transistor 110 (as dashed line 110 shown in FIG. 1) will turn on the NMOS transistor 108 to bypass the ESD current. On the contrary, when with the ESD voltage received by the pad 104 is lower than that received by the pad 106, a parasitic diode 112 (as dashed line 112 shown in FIG. 1) of the ESD protection circuit 100 or the integrated circuit 102 will be forward biased to bypass the ESD current. However, the performance of the ESD protection circuit shown in FIG. 1 is generally poor because the turn-on speed is rather slow.
FIG. 2 is a circuit diagram of another conventional ESD protection circuit. As shown in FIG. 2, the ESD protection circuit 200 is connected with an integrated circuit 202 and two input pads 204 and 206 of the integrated circuit 202. The pad 204 is connected to an input voltage VDD and the other pad 206 is connected to another input voltage VSS. The ESD protection circuit 200 comprises an NMOS transistor 208, a resistor 210, a capacitor 212 and an inverter 214. The drain of the NMOS transistor 208 is connected to the pad 204, the source of the NMOS transistor 208 and the substrate are connected to pad 206 and the gate of the NMOS transistor 208 is connected to an output terminal of the inverter 214. The resistor 210 is connected with the pad 204 and an input terminal of the inverter 214. The capacitor 212 connects with the pad 206 and the input terminal of the inverter 214. In FIG. 2, the capacitor 212 is a MOS transistor having its source and drain connected together. The inverter 214 includes a PMOS transistor 214a and an NMOS transistor 214b. The gate of the PMOS transistor 214a and the NMOS transistor 214b are connected together to serve as the input terminal of the inverter 214. The drain of the PMOS transistor 214a and the NMOS transistor 214b are connected together to serve as the output terminal of the inverter 214. The source terminal of the PMOS transistor 214a and the NMOS transistor 214b are connected to the pad 204 and 206 respectively.
The rise time of the resistance R of the resistor 210 and the capacitance C of the capacitor 212 is proportional to the product of R and C (i.e., referred to as the RC constant). In general, the rise time RC (conventionally between 0.1 μs to 1 μs) is much larger than the rise time of ESD current (conventionally between 1 ns to 15 ns). Therefore, when the ESD voltage received by the pad 204 is greater than that received by the pad 206, the voltage V1 (shown in FIG. 2) at the input terminal of the inverter 214 is at a low level relative to the voltage VDD. After the voltage V1 is inverted by the inverter 214, a high level voltage V2 is obtained. The voltage V2 is high enough to turn on the NMOS transistor 208 to bypass the ESD current. On the contrary, when the ESD voltage received by the pad 204 is smaller than that received by the pad 206, a parasitic diode of the NMOS transistor 208 within the ESD protection circuit 200 is forward biased and hence is able to bypass the ESD current.
FIG. 3 is a circuit diagram of yet another conventional ESD protection circuit. As shown in FIG. 3, the ESD protection circuit 300 is connected with an integrated circuit 302 and two input pads 304 and 306 of the integrated circuit 302. The pad 304 is connected to an input voltage VDD and the other pad 306 is connected to another input voltage VSS. The ESD protection circuit 300 includes a PMOS transistor 308, a resistor 310, a capacitor 312 and inverters 314 and 316. The source and the substrate of the PMOS transistor 308 are connected to the pad 304, the drain of the PMOS transistor 308 is connected to the pad 306 and the gate of the PMOS transistor 308 is connected to an output terminal of the inverter 316. The resistor 310 is connected to the pad 304 and an input terminal of the inverter 314. The capacitor 312 is connected to the pad 306 and the input terminal of the inverter 314. In FIG. 3, the capacitor 312 is a MOS transistor having its source and drain connected together. The inverter 314 comprises a PMOS transistor 314a and an NMOS transistor 314b. Similarly, the inverter 316 comprises a PMOS transistor 316a and an NMOS transistor 316b. 
Referring to FIG. 3, when the ESD voltage received by the pad 304 is larger than that received by the pad 306, the voltage V3 (shown in FIG. 3) at the input terminal of the inverter 314 is at a low level relative to the voltage VDD. After the voltage V3 is inverted by the inverters 314 and 316, a low-level voltage V4 is obtained. The voltage V4 is low enough to turn on the PMOS transistor 308 to bypass the ESD current. Conversely, when the ESD voltage received by the pad 304 is smaller than that received by the pad 306, a parasitic diode of the PMOS transistor 308 within the ESD protection circuit 300 is forward biased and hence is able to bypass the ESD current.
One major drawback of the aforementioned techniques shown in FIGS. 2 and 3 is that the amplitude of the voltage V2 for switching the NMOS transistor 208 and the voltage V4 for switching the PMOS transistor 308 is dependent on the ESD current. As the ESD current rises, the current passing through the channel layer between the source and the drain under the gate of the NMOS transistor 208 or the PMOS transistor 308 increases. Therefore, a gate over-drive problem may be caused when the current is over a threshold level, and the areas close to the drain and the channel may be destructed. Thus, the performance of the conventional ESD protection is reduced.
Another drawback is that when the ESD protection circuit 200 or 300 is turned, the conductive resistance thereof is high, and the potential between the VDD terminal and the VSS terminal may be increased. Therefore, the possibility of damage the integrated circuit 202 or 302 or the circuit devices inside is also increased since the protection efficiency of the ESD protection circuit is reduced. In other words, the improvement of the performance of the ESD protection circuit is necessary.